Two main features of conventional synchronous output buffer stages are the switching time (that is to say the time necessary for the logic circuits of the buffer to transmit a datum present at the input to the output upon the occurrence of a clock edge) and the amount of current supplied at the output, to be distributed at the input of the circuits that are connected thereto (the number of circuits connected thereto that an output is able to drive commonly being referred to using the term ‘fan-out’).
It is preferable for the switching time to be as short as possible, and for the ‘fan-out’ to be high, in particular in ‘transistor-transistor’ logic (TTL) systems or NMOS/PMOS transistor systems.
These two quantities are linked, and reducing the output impedance of the buffer increases the ‘fan-out’ and decreases the access time.
On the other hand, present systems produced using CMOS technology require a zero input current, and the communication frequencies, in particular on a Serial Peripheral Interface (SPI) bus, are becoming increasingly high. The switching time has thus become paramount in modern CMOS systems.
FIG. 1 shows an example of an output buffer, in which an inverter assembly including a pair of MOS transistors makes it possible to apply a ‘high’-level or low′-level signal to an output node SD. A pull-down NMOS transistor MN is connected between a reference voltage source VSS and the output terminal SD, and a pull-up transistor MP is connected between a supply voltage source VDD and the output terminal SD.
The pull-down MN and pull-up MP transistors are controlled by a control logic circuit CTLGo, putting them into on- or off-states depending on an activation signal (ON, /ON) and on a signal representative of the datum to be communicated.
Moreover, the control logic circuit CTLGo is configured to minimize the occurrence of short-circuits between the high reference voltage source VDD and the low reference voltage source VSS. This kind of short circuit (‘crossover conduction’) occurs when an inverter changes state when a collision takes place, during which the two transistors are simultaneously on. This produces an ephemeral consumption of a very high current.
As a result, the control logic circuit CTLGo is configured to minimize this short-circuit current by preventing one transistor from changing to the on-state before the other has changed to the off-state.
The control logic circuit CTLGo includes three-input logic gates, controlling the pull-up transistor MP or the pull-down transistor MN, respectively. The logic gates receive the logic value of the datum to be transmitted/dataO, an activation signal ON, /ON, and the signal present on the gate of the other transistor MN, MP.
A control inverter makes it possible to apply the control voltage at a value corresponding to each transistor MN, MP, on the basis of the logic signals leaving the logic gates.
This so-called anti-collision assembly makes it possible, when switching takes place, to anticipate a transistor being off before the other transistor is turned on.
Furthermore, the pull-down MN and pull-up MP transistors are dimensioned such that their impedances in the on-state are low enough to meet requirements in terms of data access time, for a given capacitance at the data output terminal SD (for example, of a few tens of picofarads).
The data received by the buffer come from a D-type flip-flop (DFF) triggered on an edge of a clock signal CLK.
The switching period of such a buffer stage thus comprises the propagation time in the flip-flop DFF, the propagation time in the logic gates of the control logic circuit CTLGo, the delay of the anti-collision assembly, and a delay R*C stemming from the capacitance C at the output terminal SD (R being the on-state resistance of the transistors MN and MP).
From a clock edge, the propagation time in the D-type flip-flop includes (in terms of a ‘logic layer,’ representative of an elementary delay) two logic layers for generating the clock signal, and two logic layers for propagating the data signal.
The control logic circuit CTLGo, with an anti-collision assembly, introduces a delay of two logic layers for putting a transistor into the off-state, then of two logic layers for putting the other transistor into the on-state. This constitutes a total delay of eight logic layers.
In conventional buffer devices, increasing the switching speed is achieved by deactivating or by removing the anti-collision assemblies, and this produces large short-circuit currents.
Moreover, optimizing the switching speed requires very fast switching of the buffer stage transistors, from an off-state to an on-state. This makes it necessary to produce larger transistors, which have a smaller impedance in the on-state and generate even larger short-circuit currents.